x86 is the denomination of the family of Microprocesseur S compatible with the Instruction set of the Intel 8086. The various manufacturers of microprocessors for PC must maintain a upward compatibility so that old the Logiciel S functions on the new microprocessors. The architecture of the series x86 starting from the Pentium was named IA-32 by Intel.
At the origin of design CISC, the new generations were conceived more and more like Processeurs RISC, the complex instructions being transformed in the microprocessor into more elementary instructions.
This family of processors, whose Pentium is emblematic, is passing to the 64 bit. The range AMD64 (Opteron, Athlon 64, Athlon 64 X2, Athlon 64 FX, Sempron and Turion) of AMD introduce later extensions 64 bits, partially integrated a year by Intel with the instructions Intel 64 or EM64T. Intel also proposes an architecture 64 bit IA-64 completely different and incompatible, the Itanium and the Itanium 2.
Structure
The design of the range x86 stressed the upward compatibility. Thus, the successive generations of processors admit several operating processes, which differ in particular from the point of view of the access to the memory.
Access report
The possibilities of addressing report of the range x86 go up with the 8080, which had 16 bits of adress bus and could thus reach 64 Kio of memory.
The 8086, to facilitate the passage of the 8080 to the 8086, introduced segmented addressing, where the address referred by segment: offset is segment · 0x10 + offset , with segment and offset both out of 16 bits. That provides 1 Me of addressable memory, divided into segments of 64 Kio, a segment beginning all the 16 bytes. The processor has 4 register S of segment: for the code, for the data, for the pile and additional (which are used inter alia destination in the instructions of copy as character strings). Intel introduces “models report”. In the model tiny , which imitates the model report of the 8080, all the registers of segments have the same value and one thus reaches indeed 64 Kio of memory. It is the model used, under DOS, by achievable the .com. In model small , the registers have different values but do not change: there are thus 64 Kio for the code, 64 Kio for the data, 64 Kio for the pile. To handle more memory, it is necessary to make accesses “far”, i.e. to go to seek the word in memory by initially changing the value of the register of segment, then by reading the segment with the desired offset. The “broad” model made accesses far in the code and the data and thus uses indeed the addressable mébi-byte of space. The models compact medium (64 Kio of data, several segments of code) and (several segments of data, 64 Kio of code) are compromises.
The 80286 breaks the barrier of 1024 Kio by introducing the Mode protected: the segments do not refer any more to the address segment ·0x10 but with a table (the GDT -- or the LDT) which maintains in more information of protection. Addressable space is of 16 Me, virtual space is potentially of 1 Gio, a segment cannot exceed 64 Kio. With the 386, Intel introduces a processor 32 bit. The segments can be as large as all addressable space, is 4 Gio. The pagination comes to be added to the segmentation.
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