Programmable logical circuit

A programmable logical circuit , or programmable logic network , is a Integrated circuit logical which can be reprogrammed after its manufacture.

It is composed of many elementary logical cells freely gatherable.

This type of Electronics component is commonly indicated by the Sigle S English:

FPGA ( field-programmable spoils array , network of programmable doors in-situ),
PLD ( programmable logic device , programmable logical circuit),
EPLD ( electrically erasable programmable logic device , erasable programmable logical circuit electrically),
CPLD ( complex programmable logic device , logical circuit programmable complexes),
STAKE ( programmable array logic , programmable logic network),
PLA ( programmable logic array , programmable logic network),
etc

Although basically synonyms, these terms are generally not interchangeable in the commercial vocabulary of the manufacturers: FPGA indicates rather components with technology RAM, EPLD of the components with technology FLASH, STAKE of the components with fusible technology (see § proceeded technological).

Material architecture

The programmable logic networks are circuit S made up of many elementary logical cells freely gatherable.

Those are connected in a final or reversible way by Programmation, in order to fulfill the desired numerical functions. The interest is that same a chip can be used in many different electronic systems.

Certain models can also comprise: memory of general use, blocks " DSP " cabled, of the loops to locking of phase for the generation of Clock.

FPGA

The majority of the large modern FPGA are based on cells SRAM as well for the routing of the circuit as for the logical building blocks to inter-connect.

A logical building block in a general way makes up of a table of correspondence (LUTE or Look-Up-Table ) and of a Bascule ( Flip-Flop in English). LUTE is used to implement logical equations having generally 4 to 6 entries and an exit. It can however be regarded as a small memory, a Multiplexeur or a Shift register. The register makes it possible to memorize a state (sequential machine) or to synchronize a signal (pipeline).

The logical building blocks, present in great number on the chip (of a few thousands to a few million in 2007) are connected between them by a matrix of configurable routing. This allows reconfiguration at will component, but occupies an important place on silicon and justifies the high cost of components FPGA. The topology is known as " Manhattan" , in reference to the streets with right angle of this district of New York.

The current densities do not allow any more one manual routing, it is thus an automatic tool of placement-routing which makes correspond the logic diagram desired by the originator and the material resources of the chip. As the travel times depend on the length of the connections between logical cells, and that the algorithms of optimization of the placer-routers are not deterministic, the performances (frequency max) obtained in a FPGA are variable from one design to another. The use of the resources is on the other hand very good, and of the occupancy rates of the logical building blocks higher than 90% are possible.

As the configuration (routing and Lutes) is made by points volatile memory, it is necessary to safeguard the design of the FPGA in an external, generally a Mémoire Flash series, compatible nonvolatile memory JTAG. Certain manufacturers are characterized however by the use of cells EEPROM for the configuration, eliminating the recourse to an external storage, or by a configuration by anti-fuses (the programming by high tension made " claquer" dielectric, creating a contact). This last technology is not however reconfigurable.

Some particular functionalities available on certain components:

additional blocks of memory (out of LUTE), often double-port, sometimes with mechanism of FIFO,
cabled multiplieurs (expensive to implement out of LUTE), even blocks multiplieur-accumulator for treatments DSP,
heart of Microprocessor hidden (known as hardware core ),
blocks PLL to synthesize or resynchroniser the Clock S,
partial reconfiguration, even in the course of operation,
encoding of the data of configuration,
sérialiseurs/désérialiseurs in the input-outputs, allowing connections series high-flow,
impedance controlled numerically in input-outputs, avoiding many passive components on the chart.

CPLD

The STAKE, GALL, CPLD and EPLD, of older design, use " macrocellules" logics, made up of a combinative network of doors And OR in order to implement logical equations. Bascule S are available only in the blocks of input-output. A component contains few tens to a few hundreds of macrocellules.

As the routing is fixed, the travel times are limited and allow a frequency of operation high and independent of the design. On the other hand, the use of the resources is not optimal (any term not used in a logical equation is equivalent to lost doors), with utilization ratios from approximately 25%.

One distinguishes the CPLD from the other PLD because they contain the equivalent of several components PLD, connected by a matrix of interconnection.

Applications

The FPGA are used in various applications requiring of numerical electronics (telecommunications, aeronautics, transport…). They are also used for the prototyping of ASIC.

The FPGA are generally slower, more expensive with the unit and consume more energy that their equivalent in ASIC (Application Specific Integrated Circuit). However, they have several advantages:

time to market shorter, because they are standard components,
time of shorter development, because basic functions are re-used and the reconfigurability authorizes a less strict preliminary validation,
lower cost for small series (less than 10.000 units). With the technological change, this quantity tends to increase: indeed, the price of a chip is proportional to its surface, which decreases with the intricacy of engraving, while the initial costs to manufacture a ASIC (design, tests, masks of engraving) are in strong increase.

It is sometimes possible to directly transform a FPGA into a version ASIC faster, less expensive and consuming less (because the matrices of routing are replaced by a fixed layer of metallization).

Several modern FPGA have the possibility of being reconfigured (one speaks about configuration when it is about programming of the material) partially with the flight. This makes it possible to obtain reconfigurable systems - for example a central processing unit whose instructions change dynamically according to the needs.

The modern FPGA are rather vast and contain sufficient memory to be configured to lodge a heart of processor or a DSP, in order to carry out a software. One speaks in this case about Processeur softcore, in opposition to the microprocessors hardware-core hidden in silicon. Today, the manufacturers of FPGA integrate even one or more hearts of processor " hardware-core" on the same component in order to preserve the configurable logical resources of the component. This does not exclude the utilisaton from Processeur softcore having many advantages. Worms of the " are thus tightened; Systems One Chip" , as for the Microcontrôleur a few decades ago, with in addition to configurable logic according to the user. The memory of all the last FPGA is still insufficient to carry out a little complex embarked software and one must have recourse to storages external (ROMANIAN, RAM). However, the law of Moore is not yet breathless and those should be integrated in a few years and will suffice for most of the embarked applications.

Design of the logic diagram

In order to be able to finalize a FPGA, it is necessary to use a material Langage of description (HDL) or a graphic tool for seizure. After compilation of this description, one obtains a file of configuration for the selected FPGA. VHDL and Verilog is the two most widespread languages of description.

Technological processes

The basic technological processes for the programmable components are the following:

SRAM - ( Static Random Access Memory ). Programmable at will and in-situ. Usually in technology CMOS.
EPROM (UVPROM) - ( Programmable Electrically Read-Only Memory ). Can be unobtrusive (and reprogrammed) by exposure to the ultraviolet rays. Technology CMOS, in the course of disappearance with the profit of the EEPROM.
EEPROM - ( Programmable Electrically Eraseable Read-Only Memory ). Can be unobtrusive and reprogrammed at will. Some can be programmed in-situ (often by a connection JTAG). Technology CMOS.
Flash - ( Flash-erase EPROM ). Same properties as EEPROM but with a higher density (thus with a lower cost for a given complexity). Technology CMOS.
Fusible - Programmable only once. Bipolar technology .
Anti-fuse - are programmable only once. Technology CMOS.

In the case of technologies with memories (SRAM, EEPROM, flash), the memory is located beside the logical circuit itself and each one of its bits controls a Interrupteur (in fact, a Transistor) of configuration of the logic network. In the case of technologies with (anti) fusible, those are directly in the logic network and have at the same time the function of memory not-bird and switch.

The top-of-the-range FPGA are with the point of technology: the technological jumps, like the smoothness of Engraving, are often carried out on these components before passing to the Microprocesseur S. Indeed, the repetitive structure of the logical matrix is favourable with the adjustment of the machines of microelectronic engraving. Thus, the first components engraved with a smoothness of 90 Nm were the FPGA Spartan3 de Xilinx, in 2003.

Manufacturers

Among manufacturing such programmable circuits, one finds Xilinx, Altera, Lattice Semiconductor, Actel, Cypress, Atmel and QuickLogic.

See too

Internal bonds

numerical Integrated circuit
VHDL, the language of synthesis and simulation of numerical electronics

External bonds

Introduction to FPGAs
FPGA tutorial
bases of the FPGA by Ray Andraka
Architecture off FPGA Tutorial
salesmen of FPGA:

Xilinx
Deteriorated
Lattice
Actel
Cypress
Atmel
QuickLogic
Nallatech

Applications:

Opencores : site of development of hardware open-source by using FPGA
Fpga4Fun: various projects fpga
LEON3 processor Sparc open-source produces by using FPGA

Random links: