PowerPC 620
The PowerPC 620 was a Microprocesseur RISC 64 bits based on architecture PowerPC, developed jointly by Apple, IBM and Motorola. It forms part with the PowerPC 602, PowerPC 603 and PowerPC 604 of the second generation of PowerPC (or G2). It was hardly used by some prototypes of Bull before being abandoned.
Structure
Intended for the work stations and the systems Multiprocessor S, PowerPC 620 was first PowerPC with architecture 64 bits. It could carry out four instructions per cycle of clock. It had two calculating units in entireties, two units of floating-point calculation and two units of management of the connections. It integrated 7 million Transistor S and, in spite of its frequency lower than the PowerPC 604 (133 MHz), it was much more powerful than this one.
Characteristics
PowerPC 620
- date of introduction: September 1994
- intricacy of engraving: 0,5 Micrometer S
- number of Transistor S: 7 million
- size: 311 mm ²
- Frequency: 133 MHz
- voltage: 3,3 V
- registers and way of data 64 drunk bit
- of addressing 40 bit, data bus 128 bit (2 X 64)
- size of the Mémoire hiding place:
- performances: SPECint92: 225/SPECfp92: 300
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