The PowerPC 601 a Microprocessor RISC 32 bits founded on architecture PowerPC, developed jointly by Apple, IBM and Motorola. Its architecture derives from architecture POWER (Performance Optimized With Enhanced RISC structures) of IBM. It forms the first generation of PowerPC (or G1).

History

The development of PowerPC 601 by IBM and Motorola started in 1993. It was marketed starting from March 1994 and functioned at a frequency of 50 or 66 MHz. A few months later, other models are marketed, with frequencies of 66,75 and 80 MHz. End 1994 leaves an evolution the 601, the 601v, engraved more finely and consuming less energy. The 601v had frequencies between 100 and 120 MHz.

It was manufactured by IBM, and it is Motorola which took care of the distribution. It was mainly integrated in the first Power Macintosh of Apple: Power Macintosh 6100, 7100,8100 then 6200,7200,8200 (PowerPC 601v).

Structure

First processor PowerPC 32 bits, PowerPC 601 was designed like a bridge between architectures Power and PowerPC, and integrates a bus 60x developed for the processors Motorola 88000. This hybrid character enables him to carry out the majority of the instructions POWER and PowerPC.

It can simultaneously treat three instructions per cycle of clock thanks to a pipeline, and integrates three units of execution:

• the treatment unit of entireties (FXU);
• the treatment unit of floating (FPU);
• the treatment unit of connections (BPU).

It also has an unit of management of the memory and a capacity of car-test.

Characteristics

PowerPC 601

• date of introduction: March 1994
• intricacy of engraving: 0,60 micrometer
• number of Transistor S: 2,8 million
• size: 121 mm²
• Frequency: 50,60,66,75 or 80 drunk MHz
• addressing 32 bit, data bus 64 bit
• frequency of the drunk: half of the frequency of the processor
• size of the Mémoire hiding place: 32 Kio of level 1
• voltage: 3,3 V
• consumption: 6,5 W with 50 MHz
• performances (model 66 MHz): SPECint92: 60/SPECfp92: 70

PowerPC 601v

• date of introduction: November 1994
• intricacy of engraving: 0,50 micrometers
• number of Transistor S: 2,8 million
• size: 74 mm²
• Frequency: 100,110 or 120 drunk MHz
• addressing 32 bit, data bus 64 bit
• frequency of the drunk: half of the frequency of the processor
• size of the Mémoire hiding place: 32 Kio of level 1
• voltage: 2,5 V

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