Material language of description

See also: HDL

A material language of description ( HDL for hardware description language in English) is, in electronic, a data-processing Langage allowing the formal description of an electronic circuit. This one can describe the operations of the circuit, its design, and test by means of simulations that operation is well that awaited.

A HDL describes in the form of text the temporal behavior and/or the structure (space) of the circuit of an electronic system. With the difference in a software computer programming language, the syntax and the semantics of a HDL include explicit notations to express the time and the parallelism which are the principal attributes of the material. One names netlist ( list of connections in English) the languages whose only characteristic is to describe connections of a circuit between its various hierarchical blocks.

Languages of HDL

Languages of purely numerical description, various degrees of abstraction.

Advanced Boolean Expression Language (ABEL) low directed level;
AHDL (Deteriorated HDL) language owner primarily structural near of ABEL;
Verilog which mixes structural and algorithmic description;
VHDL slightly more abstract than Verilog which is inspired by ADA;
SystemC using the C++ and which makes it possible to model the interactions software/hardware.

The mixed languages, which are often extensions of the precedents. It allow the modeling of the systems using differential equations.

Verilog-AMS;
VHDL-AMS ;
Modelica language of modeling general practitioner directed object.

Other languages, without being fully HDL are used for description structural of circuits or their analogical behavior.

netlist SPICE (the historical simulator of circuit on the level transistor);
netlist EDIF, the neutral interchange format (standardized and not owner) of the electronics industry;
files IBIS, allowing to describe the analogical behavior of the digital interfaces of circuits.

See too

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