K10

K10 which one knew under the name K9 or K8L before is the name of the new family of Microprocesseur of AMD which will leave to compete with the Core 2 Duet and future Penryn of Intel. K10 marks the ninth generation of processors of AMD. The exit is planned for the re-entry 2007 is 4 years after the introduction of K8 architecture to the particularly long commercial lifespan for an architecture processor.

For AMD, to mark the blow with K10 concerns the urgency. Indeed the financial results are bad and the margins decrease since the only way for AMD of resisting the current architecture of Intel is to break the prices (for example Athlon x2 64 5600+ passed from 505$ to 188$ in a few months after three consecutive falls.). Thus the margins passed from 58,5% to 28,1%.

Nomenclature

AMD thus passes from its architecture K eighth of the name to a K10 architecture. K9 was cancelled after 6 months of development.

It as should be known as before AMD publishes officially this name of K10 by the voices of Giuseppe Amato and Philip G. Eisler (respectively chief technical officer of the Sales and marketing for Europe and vice-president of division chipset of AMD) in February 2007, the specialized press logically allotted name K8L to the new architecture of AMD. The Inquirer thought whereas the " L" referred to the Roman numeral meaning 50, it would act then of K8.50, that is to say a version halfway between architecture K8 and K10. It appears in the interview of the persons in charge AMD who the K8L was a denomination for processors of K8 architecture for portable PC in 65nm.

With this new architecture, AMD gives up the P-Rating (index of performance) introduced with the Athlon XP into 2001 which made it possible at the beginning to place Athlon XP vis-a-vis Pentium IV of Intel and which with the passing of years became increasingly whimsical, especially since the beginning of the era multicore. Thus AMD returns to an indication of the real frequency. K8 will be indicated for example " Athlon X2 3600+" , against " Phenom X4 GP 6xxx" for K10.

It is also possible that AMD has resorts to a denomination close to the denomination of the CPU Intel for its K10. Indeed, this new denomination is already planned for Athlon 64 K8. One will then find a couple of letter to qualify the type of CPU and a quartet of figure to indicate the CPU in the range.

History

Rumors

In April 2003 whereas first K8 are not even on the market, the Russian site anglophone digit-life transmits the first rumors on the new news generation of processors of AMD, the French-speaking sites will relay the rumor and here is in substance what was announced for the new architecture of AMD:

Controller DDR-II integrated,
improvement of the prediction,
3 pipelines x87 (FPU), 3 SE and 2 pipelines of calculations on the entireties (ALUMINUM). Possibility of marrying by 3 decoders of instructions (FPU + SE + ALUMINUM). ,
Introduction of a new type of mask: a kind of L0 which could be incarnated in the form of 4ko of mask before and after pipeline FPU to make the operations continuous,
a pipeline ALUMINUM of 15 levels, and a pipe FPU of 20 levels,
Fonctionnement of the mask of instruction (I-mask) and decoder with 2 times the speed of clock,
Intégration of a L3 mask,
Arrivée of Hyper Transport 2.0, connections to 1Ghz and Octal mode “Went back Spleen” (8x) for a theoretical maximum flow to 25Go/s,
Amélioration of protocol MOESI for a better coherence in the management of the mask in a system Multi-CPU or multi-core.
Division of the units of possible execution between two core or CPU thanks to bond HT 2.0.

on October 15th, 2003 with the forum of the microprocessor with San Jose in California, Fred Weber, the chief technical officer of AMD lets escape that K9 will be available to the second half-year 2005 and will have several cores. Rumors much more whimsical also circulate. One then hears of an architecture multithreadée as at the PIV of Intel which would reach the 10GHz, which would consume less thanks to one intelligent management of energy, etc

In August 2004 , the rumors are done more pressing. The specialized press announces the quad-core and a launching for 2007.

In April 2006 , after one year 2005 calm on the level of the rumors, a revolutionary innovation seems to appear in new architecture AMD: the reversed hyperthreading where the possibility of not having of only one core logical with a multitude of cores physical, is exactly the opposite of the technology of Pentium IV with hyperthreading.

All these rumors were however not confirmed by AMD which remained entirely dumb during this period.

Confirmations

In March and June 2006 , the interviews of the executive vice-president of AMD Henri Richard hardly bring more information; the person in charge being very vague. But these interviews mark the end of the silence of AMD.

In the first interview with digitimes, the journalist questions it on the persistent rumors of next generation of processors which Mr Richard answers that it is sorry to be able to give more information because of the ultra competition of the sector and to add only that next architecture will be turned towards the multi-core, which represents for him the future.

In the interview of June, Henri Richard is less evasive when the journalist asks for the prospects of AMD to him over the three years to come. Thus he declares that the architecture which aims at replacing K8 will arrive well in 2007 and that the improvements are numerous: increases in the performances of calculations of entireties (ALUMINUM) and of floating calculations (FPU), band-busy memory, interconnections and well of others (what appears obvious for a new architecture). He concludes by an equestrian metaphor: We are clearly engaged in a race with two horses. And as you can expect it in a race, sometimes, when a horse has a light advance compared to the other, that reverses the situation. But what is important it is the race .

Always in March 2006 , one learns code names from the future processors of the K10 range in Spring Processor Forum. Thus it will be Deerhound in the second half of 2007 then Zamora in the second half of 2008 for the waiters; Cadiz for the work stations and Greyhound for the personal computers in the first half of 2008.

In June 2006 , with the AMD Technology Analyst Day, of the precise details appears on the size of the mask, the hypertransport and the energy management:

Mask

L1D: 64ko for each core,
L1I: 64ko for each core,
L2: 512ko by core,
L3: 2Mo divided.

Moreover latency is re-examined with the fall compared to K8 architecture and the doubled band-width (2x16 bytes/cycle, against 2x8 before).

Hypertransport

The next generation of Opteron will have four Hypertransport bonds functioning each one I usqu' with 2.6GHz is 83,2Go/s of band-width, against three bonds functioning with 1GHz for 24Go/s of band-width for K8 architecture. These bonds could dynamically be reconfigured in bonds 8-bits. Thus it will be possible to connect up to 8 sockets between them for a total of 32 cores of execution. In the event of interferences the hypertransport tightened from now on capable of reconnecter of him even after an interruption.

Energy

The new generation of processors AMD thus sees the appearance of technology Dynamic Independent Core Engagement . Behind this name the faculty of an individual energy management of each core is hiding place. Thus in the event of weak use, the regulation of the tension will be able to intervene to put in day before one or more cores processor. This in order to optimize energy consumption. The cores will be able to manage their frequency and their stension independently of from/to each other. The northbridge (intern with the CPU) will have to him also its separate control of tension. Controller DDRII will be able to put himself in day before to save energy, it will be able to also decrease the frequency of the RAM. All the internal “bodies” of the CPU can be put in day before some is the state of the CPU, when they are not requested any more. FPU, ALUMINUM,…

At the summer 2006 , Dirk Meyer, the president and operational director of AMD (Chief Operating Officer) announces (at the same time as disappointing financial results) that the quad-core of the SunnyVale firm will be well launched semi-2007 and that the first demonstrations of the new generation of processor will take place at the end of 2006. In August is also learned that Opteron of the K10 generation arrived in final stage of development and that they are " taped-out".

In October 2006 , other precise details make their appearance.

calculating unit SE and floating-point calculations.

Width of 128 bits for the calculating unit SE of Barcelona against 64 bits for current processors AMD. Execution of two operations SE and a displacement SE by cycle of clock. One also speaks about performances doubled for the unit dedicated to floating-point calculations. Levelling of instructions SE with the SE (derivative of instructions SE from Intel). AMD seems thus very close to Intel on the management of instructions SE.

Prediction

Improvement of the “predictions of connection”, with in particular the possibility for the processor of carrying out certain instructions in the disorder (Out-Of-Order) in a more effective way.

independent controllers report.

The die has from now on two controllers report independent of 64bits against only one of 128bits for K8. Theoretical management of 256To of memory thanks to an addressing 48bits. (Management 48bits was already present on the last revision F of K8)

In December 2006 , with the semi-annual AMD Technology Analyst Day, the roadmap of AMD is specified. All the family of K10 processors known as " Stars" appears. As well for waiter with CPUs Barcelona or Budapest, as for the machines desktop with the marking clerks Agena FX, Agena, Kuma and Spica; and for the portables with the Griffin hearts. AMD thus still changed the name of its hearts K10, one attends the waltz of names.

Griffin is based on two K8 hearts, but will integrate functionalities of K10. Budollzer is the successor of Griffin is planned for the second quarters 2008 and will be based on of K10.

Technologies and characteristics

Engraving

The first microprocessors of the K10 generation will be exclusively engraved thanks to the technology of engraving in 65nm of AMD in partnership with IBM which uses wafers ONESELF (Silicium on insulator) 300mm UNIBOND™ of the French manufacturer Soitec who maintains a privileged partnership with AMD. The partnership with IBM also makes it possible AMD to use SiGe technology from IBM (germanium addition in addition to silicon in seen to make the transistors more powerful). These microprocessors will be surely manufactured in the factory Fab 36 of AMD in Dresden in Germany which manufactures already Athlon 64 in 65nm. The factory will be able to produce normally in the neighborhoods of 100 million processors per annum since 2008 (for 20.000 wafers) what coincides with the arrival of K10 architecture. AMD uses for its engraving in 65nm its technologies Continuous Transistor Improvement (CTI) or continuous improvement of transistor and Shared Transistor Technology (STT) or technological division of the transistor as well as technology Dual Stress Liner (DSL).

There will exist perhaps thereafter K10 processors engraved into 45 even in 32nm (Deneb FX, Deneb, Propus, Regor and Sargas), since AMD intends to produce processors thanks to the technology of lithography per immersion since 2008.

Memory

The processors of the K10 family just like their K8 predecessors will have their controller report integrated contrary into the Intel processors which leave this load to the chipset. This characteristic was partly responsible for the success of Athlon 64 by reducing latencies considerably for the access to memory RAM when the standard was the DDR-SDRAM first name. Indeed with this type of bars, latencies of the RAM were of 2-2-2-5 for the best DDR400. But during the introduction of the DDR2, the asset of Athlon 64 attenuated because latencies exploded and the increase in frequency could not that to compensate for this fall of performance. Thus Athlon 64 on socket AM2 are just as powerful as Athlon 64 on socket 939. Latencies memories having seriously to decrease, the DDRII does not pose any more a problem. K10 will be made to support DDR2 1066MHz out of standard. The waiters will exploit the DDR2 800 initially.

The next revisions of heart of the family K10 (Deneb FX, Deneb, Propus, Regor and Sargas) planned for the year 2008 even 2009 will be they, turned towards the memory DDR3 and the 45nm which is not yet on the market. They will be equipped with 4 or 6Mo of L3 mask.

Sockets

AMD made the choice of a certain continuity at the time of this passage to K10. There will thus not be as at the time of the passage of K7 architecture in K8 a radical change of socket (then socket has towards socket 754 then 939 and AM2). AMD thus named the socket of its new processor AM2+ to mark the proximity with socket AM2. Socket AM2+ will thus accommodate all the K10 processors except for the processors socket 1207 incompatible. It is about a socket of 940 pins. The differences between socket AM2 used currently for K8 and socket AM2+ will be the management of the hypertransport 3.0 by this last and the advanced management of energy since each heart will have clean Vcore. On socket AM2, the processors will be able all the same to vary their frequencies independently but not them vcore. There is retro compatibility and one will be able to benefit from K10 architecture on a mother chart AM2.

The chipsets for already announced AM2+ are Nvidia Nforce 7 code name MCP72, it VIA KT960 and KM960 but also the chipsets of ATI (now property of AMD) RD790+, RD780, RS780, RX780, RS740 and RX740.

K10 socket AM3 will probably have two controllers report, a DDR2 and a DDR3 thus they will function perfectly with a mother chart AM2+. However this information is to be put between tweezers, AMD could change opinion very well because the cost out of transistors of two controllers report could be high.

K10 AM2+ will not be compatible AM3.

Specifications

The complete characteristics of K10 are those of the first K10 heart, namely Barcelona. The versions desktop will undoubtedly be different since Barcelona is made for the market waiter with the particular requests.

General information.

Two controllers integrated report DDR2 (the controller report 128bits of K8 is separate in two controllers 64bits for K10. Passage envisaged with a controller report DDR3).
Frequency of operation between 1900 and 2600MHz (the versions desktop should reach the 2800MHz).
16 levels of pipeline.
Management of the hypertransport 3.0 for buses beyond 3GHz (on socket AM2+, socket AM2 the function will not be exploited).
mask.

64ko of mask L1D by core (Size identical to that of K8)
64ko of mask L1I by core (Size identical to that of K8)
512ko of L2 mask by core (Size identical to the K8 last. Kentsfield offer 2x4Mo of mask L2 and the Penryn future until 2*6Mo).
2Mo of divided L3 mask.
possible Extension until 8Mo, 4 with 6Mo with the passage to the 45nm: core Shangai .

the die.

1^er quad-core known as " natif" product bulk (It is not a question of the juxtaposition of two dual-core as for the first quad-core Intel.
Composed of 11 layers of engraving (Against 9 for K8 and 8 for the core2duo. That makes the manufactoring process a little more complex but does not change anything for the user. Intel used also this type of process with as many layers it y' has a few years).
463 million transistors (Vis-a-vis the 582 million Kentsfield but engraved on two die. This is explained by the fact why Kentsfield embarks 8,25Mo of mask whereas Barcelona is limited to 5.5Mo).
60 million transistors not-masks (that is to say 30%) in more compared to K8.

improvements of the pipeline and new Instructions.

the SE 128,

Management of instruction a length of 128bits (Against 64bits for K8).
parallel Management of 32 bytes per cycle (Either double of with K8. Improvement which could profit with other types of operations such as for example on the entireties).
Two loadings of instructions per cycle since the mask L1 (stable Number compared to K8 but thus twice more data charged by cycle because of the passage of instructions 2*64 to 2*128bits).
Interface widened between the L2 mask and the controller report with 128bits (For the coherence of architecture, cad to avoid a bottleneck).

Introduction of instructions SE.
Extentions of instructions SE: EXTRQ/INSERTQ and MOVNTSD/MOVNTSS.
Appearance of instructions LZCNT and POPCNT used in cryptography.
Reduction in latency on divisions of entireties (ALUMINUM) (the practical consequences should be tiny)
4 FPU (Floating Point Links, calculating units to floating decimal point) (instead of 2 for K8. AMD speaks about a theoretical improvement of +300% of the performances vis-a-vis Dual Core K8 (twice more cores with twice more FPU, therefore quadrupled performances), but finally in practice the improvement would be about 50% vis-a-vis competition).
Fastpath.

the microinstructions CAL and RET-Imm are now instructions which use Fastpath (they are not microcoded any more).
displacements between registers of the entireties and registers SE of the MOVs instructions use also Fastpath.

Subsystem report, mask and prefetch.

Reduction in latency on the level of the mask.
Better data management Out-Of-Order .
Predictions,

Appearance of a preacher of indirect connection: 512-entry indirect predictor (Intel had added this type of preacher on its PIV Prescott which suffered from their long pipeline and any error of connection represented a considerable waste of time).
the space dedicated to the " crush retour" ( return stack ) is multiplied by two.
the direct prediction is also improved by the increase of the data " historiques" (Possibility offered by the size gained with the passage to the 65nm whereas K8 architecture was satisfied at the beginning with the 130nm).
Sideband Stack Optimizer equivalent with the Dedicated Stack Manager of Intel.

TLB (Translation Lookaside Buffer)

Extension.
physical Addressing 48bits allowing the management of memory until 256To

Prefetch:

2 prefetch by core, for the data and for instructions (AMD preserves the number of prefetch of K8. It should be noted that the C2D from Intel have three by core of them).
the prefetch load in the L1 mask (the prefetch charged in the L2 mask at K8).
Appearance of a prefetch of RAM using its own mask.

Virtualisation.

Virtualisation of the memory Nested Paging

Energy.

the voltage of the northbridge is now independent and spreads out 0.8V with 1.4V
Apparition of the DICE or Dynamic Independent Core Engagement or material management of the PowerNow! allowing management independent of the frequency of each heart.
TDP ranging between 95W and 120W (TDP between 45W and 89W for Phenom, unknown TDP for Phenom FX)

Registers

additions of 8 registers additional for the 64bits.

Performances

During a demonstration on November 30th, 2006, AMD announces and shows with the press which Barcelona will be overall 40% more powerful than a Xeon 5355 (Quad-core with 2.66GHz). Lately AMD affirms that its processor should precede the performances of Xeon Quadcore of 50% on floating-point calculations and 20% on calculations related to integers. However, it is good to specify that such a comparison cannot be checked yet and that this comparison applies for equal frequencies between the processor of K10 architecture of AMD and Xeon from Intel. Moreover they are there only theoretical tests.

At the beginning of May 2007, AMD made a new rather impressive demonstration of its K10 futures. It is with CTO Technology Summit in Monterey, in California that AMD revealed a machine having two processors K10 quad-core. The machine of 8 cores was capable of encoder to the flight, i.e. in real-time, a video 720p (1280*720) and a 1024p

Family of processor

All the range of AMD will pass in little time to K10 architecture. One will find known denominations and new names. The Opteron for waiter Bi and quadri processor known under the name of code Barcelona will be first K10 with having to prove reliable, a second core Budapest will come to reinforce the Opteron range on the market of the waiters plain-processors. The general public will have the choice between Phenom X4 (Agena), and Phenom X2 (Kuma). The denomination disappearing Athlon 64 (for the high-end), any confusion between K8 and K10 disappears. One will also find versions FX and Low power. Athlon x2 64 ( Rana ) will constitute the bottom-of-the-range offer dual-core, the sempron ( Spica ) will be only the K10 mono-heart, and Turion ( Griffin ) will be dedicated to punts forms portable.

Table carried out on information of roadmap AMD and Clubic (Opteron) and (desktop)

Opteron

Opteron is the version of K10 intended for the waiters, and the work stations. Version SE are the top-of-the-range versions of the series with the TDP of 120W, the versions standards have a TDP of 95W and the version HE ( High Efficiency ) is the versions which profit from a TDP reduced to 68W.

" Star' S Family"

The new range desktop of AMD thus breaks up into " Phenom FX" for the very top-of-the-range one (which will be surely a simple renaming of Opteron), " Phenom X4" for the high-end and " Phenom X2" for the average range, " Athlon 64 X2" for the bottom-of-the-range one and " Sempron" for line entry AMD.
The frequencies spread out between 1900 MHz and 2800 MHz and the TDP between 45 W and 89 W.
The number of core varies from 1 for the " Sempron" to 4 for the " Phenom FX" and the " Phenom X4" while passing by 2 for the " Phenom X2" and the " Athlon 64 X2".

Turion

AMD will not strictly speaking leave Turion K10 at the end of 2008 even 2009 and the introduction engraving in 45nm. With Turion Griffin , AMD will propose very reduced K10 which will have only the energy improvements of the DICE. With its Griffin , AMD will also propose a platform: Puma . It will use a graphic heart supporting the directX 10 and a UVD (Universal Video To decode).

Internal bonds

External bonds

Article of The Inquirer, which brings back the remarks of Giuseppe Amato (Technical Director, Sales and Marketing EMEA of AMD)
Further AMD next-gen specs roll out (The Inquirer, list of the K10 processors to launching)
December 2006 Analyst Day of AMD: roadmap official of AMD.
Barcelona Structures: AMD one the Counterattack (re-examined detailed of K10 architecture by anandtech)
Anandtech, CeBIT 2007: Storage & Servers - AMD, performances and indications on Barcelona in CeBIT 2007.
the 21 variations desktop of K10
Architectures of the processors, preliminary version and old (2001) of a course of MADE IRIDESCENT (Research institute in data processing and systems random) but very complete.
AMD K8 - Part 3: Structure, to include/understand K8 architecture allows to include/understand the K10 architecture which is a great evolution more than one revolution.
New nomenclature AMD (InfoMars.fr)

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