JTAG

JTAG for J oint T is has ction G roup is the name of the standard IEEE 1149.1 heading " Standard Test Access Port and Boundary-Scan Architecture" . The JTAG was standardized in 1990.

Term JTAG, indicating the work group which conceived the standard, (but very largely) is wrongly used instead of the generic term Boundary Scan , or of the initials TAP ( Test Access Port , wearing of access of test).

Principle

The technique of Boundary-Scan (literally, examination of the borders ) is conceived to facilitate and automate the test of the numerical electronic charts. It consists in giving an auxiliary access to the pins of input-output of the strongly integrated numerical components.

Initially, Boundary Scan was only intended for the test of short-circuit and continuity between compatible chips. Knowing the electric Diagram of the electronic Chart, one applies a whole of logical signals (called vector of test) to the pins of entry of certain components, and one records the logical levels on the pins of exit of the components which are connected there, to make sure that they correspond to the awaited values. One can thus make sure of the good quality of the tracks of the Printed circuit and the welding S.

For that, each pin of input-output is not connected directly inside the numerical component, but through a " JTAG" cell; allowing to control it independently of its initial function. It is thus possible to configure it in entry (high-impedance) or exit (logical high or low Niveau). The cells are connected between them by a bus series making it tower of the chip (from where the concept of " frontière" or Boundary ), equivalent with large a Shift register of size equalizes with the number of pins of input-output of the component. The TAP Controller, which receives signals JTAG of outside, makes it possible to activate and control the cells according to a standardized sequence.

Applications

The JTAG is not limited to the tests of continuity. It is indeed also possible to test combinatory logic functions , even if they are made up of chips noncompatible JTAG, by working out suitable vectors of test and provided that the entries and exits of these functions are connected to components JTAG. In the same way, it is possible to test memories while writing then reading again values of test. It is even possible in this manner of programming memories not-birds (EEPROM and Flash).

Moreover, the JTAG is not limited to external connections to the component. Standard JTAG is thus used to replace the emulator S of Microprocesseur S (systems of débug on chart replacing the component physically), by giving an direct access inside the processor (stagnation points, reading and writing of the Registre S interns, of the built-in memories and external…) without disturbing its interactions with outside. One names this technique ICE (Emulator In-Circuit) or ICD (Debugger In-Circuit), and it is omnipresent on the microprocessors and modern Microcontrôleur S.

Bus JTAG is also used to program the programmable logical components (FPGA and CPLD) as well as many microcontrôleurs (thanks to the capacity of the JTAG to program the Flash microcontrôleurs.), even for débugger a microprocessor or to reach a " analyzer logique" integrated in a FPGA.

Technology

Bus JTAG is a Bus series composed of the 5 following signals of control:

TMS, (Test Select Mode) Signal of activation of the communication JTAG,
TCK, (ClocK Test) Clock,
TDI, (Test Dated Input) Entry of the data,
TDO, (Test Dated Output) Sortie the data,
TRST, (Test Reset) Rebootstrapping. This optional signal is active on the bottom grade.

Generally, compatible integrated circuits " Boundary Scan" gone up on an electronic chart are associated to form a chain called " Chain JTAG" . One thus connects signal TDO of a component to signal TDI of the following component, so as to form a chain. The other signals are common to all the components of the chain.

It is also possible to chain between them several compatible charts JTAG, in order to carry out a test of a complete system. This technique is the extension object of standard JTAG, named IEEE 1149.5.

A component Boundary Scan can be used according to 4 modes:

EXTEST: external test, allowing to order the pins of input-output of the component in order to test inter-connected them chart,
INTEST: test interns component,
IDCODE: identification of the component,
BYPASS: put in high-impedances of the input-outputs of the component, its internal chain is reduced to a register in order to accelerate the access to another component of the chain.

The activation of a mode is made via the programming of the register IR (Register Instruction) and the use of a mode is made via the sending of data on the register DR. (Data Register) .

External bonds

Details on the operation of the bus
Site hardware-hacking.com
Diagrams of cables JTAG on parallel port of free PC
Tools to use bus JTAG

Random links: