Intel Core Structures

Name of the 8th architecture X86 of Intel.

Here recent architectures X86 Intel, by order of exit, which it succeeds.

" Core" is moreover an English name meaning " noyau" or " cœur" , and indicating in data processing the constituent whole of the structures only one microprocessor: units of decodings, prediction, of execution, hides L1 etc… The current trend is to join together several microprocessors on same a die (silicon wafer), thus constituting dual, quad or multi core. This explains the choice of Intel in the name of this architecture " Core" , like in the choice of trade names.

" Intel Core" resemble " Intel Mobile" +1 fast decoder, +1 ALUMINUM, +1 additional unit load/blind, + dedicated floating vectorial units (floating SE treated by the FPU before). The L1 mask is always of 2x32ko. One finds the fusion of micro the instructions, appeared on Pentium Mr.

Among the innovations:

"memory disambiguation" : prediction of the conflicts reports to the writing/reading (with anticipated loading-execution if the prediction does not envisage a conflict)
execution SE 128 bits in a cycle (2 cycles before)
macrofusion of the instructions (accelerates the decoding and the follow-up of instructions SE 128 bits)
division of the mask L2
selective desactivation of the units for the energy saving

Supported instructions: X86-64, XD, SE 1,2,3,3+.

Processor of Intel Core Structures:

Core 2
Core 2 Extreme
Dual Pentium Core
Xeon
Celeron

Penryn

The evolution die shrink of the Intel Core Architecture names Enhanced Intel Core Architecture. It with the characteristic to use engraving in 45nm instead of 65nm. It introduces also the new instruction SE. This evolution is not a new architecture it thus forms always part of the 8^e architecture of Intel.

Summary table of the processors based on Intel Core Structures

(p): temporarily

" Core" is moreover an English name meaning " noyau" , and indicating in data processing the constituent whole of the structures only one microprocessor: units of decodings, prediction, of execution, hides L1 etc… The current trend is to join together several microprocessors on same a die (silicon wafer), thus constituting dual, quad or multi core. This explains the choice of Intel in the name of this architecture Core , like in the choice of trade names.

Among the innovations:

"memory disambiguation" : prediction of the conflicts reports to the writing/reading (with anticipated loading-execution if the prediction does not envisage a conflict)
execution SE 128 bits in a cycle (2 cycles before)
macrofusion of the instructions (accelerates decoding and followed it instructions SE 128 bits)
division of the mask L1
selective desactivation of the units for the energy saving

Supported instructions: X86-64, XD, SE 1,2,3,3+.

External bonds

Core architecture on ArsTechnica
Core architecture on RWT
Topicality on Presence PC
Intel Core 2 Duet E6700 vs AMD Athlon 64 FX-60 (Clubic)
very complete File on Core 2 Duet (Hardware.fr)

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