HyperTransport

The HyperTransport (in the past Lightning Dated Transport or LDT) is a local series/parallel bus faster than the Bus NCV and which uses the same number of pins. HyperTransport is a technology resulting from the laboratories DIGITAL. Following the disappearance of DIGITAL, the development was taken again by AMD, IBM and nVidia which had acquired a license.

Hypertransport offers a theoretical band-width of 12,8 Go/s. the exchanges are done up to 800 MHz.
HyperTransport 2.0 offers a theoretical band-width of 22,4 Go/s. the exchanges are done up to 1,6 GHz.
HyperTransport 3.0 offers a theoretical band-width of 41,6 Go/s. the exchanges are done up to 2,6 Ghz.

Many information was disseminated in connection with the counter-attack of Intel, with in particular a bus of the same type named Common System Interface (CSI), whose characteristics remain vague and the remote coming out date (not before 2008). While waiting, the machines containing Opteron S keep the advantage for the applications which make suffer the bus report, in particular when the number of processors is large.

Use

HyperTransport technology is currently used mainly as bus report (communication between the Chipset and the Processeur) in certain architectures like the K8 (Athlon 64, Opteron,…) or certain PowerPC like the PowerPC 970 of IBM used in the Power Mac G5.

Contrary to the bus report of the Intel machines which is connected to the bus of input-outputs only in one point (the chipset Northbridge, which is thus a bottleneck), the bus Hypertransport has a switchée architecture as a network on which several chipsets can connect buses of input-outputs. For example, of the traditional mother charts for machines bi- Opteron often have a bus NCV connected to the bus Hypertransport by a bridge AMD8131 while a bus PCI Express (independent of the other) is connected in another place by a chipset nVidia nForce. Thus, a processor can reach the peripherals hidden behind one of the 2 buses of input-outputs without géner the accesses of another processor to another bus (except well-sure if the geographical location of the processors and chipsets makes that these accesses cross).

According to the number of processors and the presence of port of extension HTX, the topology of the bus Hypertransport can vary from a single bond to strange forms such as a square with only one diagonal, or from the indescribable things for the mother charts with 8 processors.

Random links: