GDR SDRAM

GDR SDRAM or Double Dated Spleen Synchronous Dynamic Random Access Memory is a type of Mémoire to Integrated circuit used in the Ordinateur S since 2003 and commonly shortened under the initials GDR. GDR provides better a Band-width than ordinary SDRAM by transferring the data at the same time on the face going up and the face going down from the clock pulses, which causes to double the speed of access to the memory, in reading and writing. This characteristic gives him its name: " Double Dated Spleen " mean " flow report double" (compared to SDR SDRAM).

Thus, a mother chart equipped with memory DDR-SDRAM and having a drunk given rhythm report with 133 [[Hertz MHz]] equivalent in flow of is given to SDRAM with 266 MHz.

The manufacturers of memory had difficulties in produce in mass of GDR to more than 400 MHz. Thus, since 2005, it is gradually replaced by the DDR-2, which functions according to the same principle as GDR, but simpler to produce, and allowing higher frequencies of clock. The DDR2 is in competition with the Rambus XDR-DRAM but should become the standard, whereas QDR (Quad Data Spleen) is too complex to be implemented.

RDRAM is an alternative to GDR SDRAM, but of many manufacturers do not use it any more.

JEDEC established standards speed for the GDR SDRAM, divided into 2 parts: the first for the chip S and the second for the memory S.

Specification of the bars memories

The memories GDR generally have a commercial name of the PCxxxx type, where “xxxx” represent the flow of information in Mo/s. Note: All the speeds of RAM not indicated in this list are not approved by JEDEC - it is about optimization of tolerance carried out by the manufacturers.

There is no architectural difference between different the GDR SDRAM designed for the various frequencies from clock, for example PC1600 (conceived to function to 100 MHz) and PC2100 (conceived to function to 133 MHz). The figure indicates simply the level of operation guaranteed for each type of memory. However, it is possible to use GDR SDRAM at a frequency lower than that envisaged (Under-fréquençage) or higher (Surfréquençage). The surfréquençage can be tried only with memories of high-quality and by experienced users (see Surfréquençage).

Flow report GDR

The flow report (and consequently the name) of a memory are calculated as follows: GDR are memories 64 bits (8 bytes). That means that barette of memory GDR can transmit:

8 * 2 = 16

bytes with each cyle of clock, factor 2 coming from " the DDR" effect;. For the example, let us suppose that this memory turns at the frequency of 133 MHz, one thus has at each second:

16 * 133 = 2128

, is an theoretical output from approximately 2100 Mo/s: it is thus of the PC2100.

Physical differentiation of the various types of memories

DIMM S of GDR SDRAM have 184 pins (whereas the SDRAM counts only 168 of them), and can be differentiated from DIMMs of SDRAM by the number of hooks (GDR SDRAM has of them one in the center, SDRAM has of them two offset). GDR functions with a voltage of 2.5 [[Volt V]], compared with 3.3 V for the SDRAM. This can reduce electricity consumption significantly.

Double Channel (dual Channel)

Certain controllers report use a double channel (in English Dual Chanel) or even quadri Chanel for the memory. It is a question of exploiting the modules of memory per pair in order to cumulate the band-width and thus to exploit to the maximum the capacities of the system by doubling or quadrupling the effective band-width. It is essential, during the use of Dual Chanel, to use identical bars per pair (frequency, capacity and preferentially of the same mark) to optimize the performances and to make it possible the chip to cross the accesses without concern.

Synchronization

The synchronization of the memory (in English timing) is a succession of cycles of clock necessary to reach a data stored in random access memory. Symbolized by 4 digits (e.g. 3-4-4-8), they correspond in the order to the following values:

CASE delay or CASE latency (CASE meaning Column Address Strobe ): it is about the number of cycles of clock running out between the sending of the reading command and the effective arrival of the data. In other words, it is about the access time to a column.
CLOSE-CROPPED Preloads Time (noted tRP, SHORT-NAP CLOTH meaning Row Address Strobe ): it is about the number of cycles of clock between two instructions SHORT-NAP CLOTH, i.e. between two accesses to a line.
CLOSE-CROPPED to CASE delay (noted tRCD sometimes): it is about the number of cycles of clock corresponding to the access time of a line to a column.
CLOSE-CROPPED activates time (noted trass sometimes): it is about the number of cycles of clock corresponding to the access time to a line.

Correction of errors

Certain bars memories have systems of correction of error in order to guarantee the integrity of the data which they contain. One finds them most of the time on the waiters especially if the handling of data is critical.

bars of memory ECC ( Error Correction Coding )

See too

dual SDR SDRAM
Channel
DDR2

External bonds

Official JEDEC website
http://www.ddrmemoryram.com/ddrsdram_and_sdram.html

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