Dual channel

Architecture with dual Channel is a technology of Mother chart making it possible to double the Band-width equivalent between the Random access memory and the controller of memory. The controllers of memory offering architecture to dual channel use two channels of data of 64 bits, thus giving a total band-width of 128 for the transfer of information of the random access memory towards CPU.

To achieve this goal, the bars of memory, in particular GDR SDRAM, DDR2-SDRAM and DDR3 SDRAM, must be inserted in a precise way on the Mother chart. Certain map productions mothers will put slits of memory at code of colors allowing visually to identify the various channels of memory. To be able to function in dual channel, the bars of memory must be identical inside the same channel on the mother chart. In certain cases, it is possible to use bars which are not identical, for example, coming different manufacturers, but they must absolutely be of the same capacity, specifications, as well as the same organization of the chips. However, several map productions mothers officially will support only the configurations in which an absolutely identical pair is used. For this reason, the majority of the manufacturers of memories now offer pairs of bars (commonly called kits ) of identical DIMM.

The introduction of this technology on the machines general publics took place in 2001 with the appearance of the chipset NForce 420 of NVIDIA. This chip being only intended for the processors AMD it will be necessary to await 2003 and the exit of the chipset Intel E7205 to be able to use the dual channel on the platforms Intel.

Intention

Architecture has channel dual of a controller report makes it possible to increase the flow of data between the microprocessor and the main memory reducing the bottleneck between the two. The controller report determines the types, capacity and speeds of each barette memory and thus determines the speed and full capacity of the memory of the system. There exist several ways of designing a controller of mémoire ; until in 2001, the most current way was the configuration with single channel. Its advantages were its low costs and its flexibility. With progress of the microprocessors, the controller became the principal bottleneck because it did not manage any more to reach the memory rather quickly to satisfy the processor.

The configuration with dual channel allows a doubling of the band-width memory. To the place of only one channel of memory, a second channel is added in parallel. With two channels working simultaneously, the effect of bottleneck is reduced. Instead of waiting until technologies of random access memory improve, architecture with dual channel optimizes simply the use of current technology. Although the implementation differs according to the types of processors AMD and Intel, the principle is the same one.

In detail, the controller of memory will be able to exploit the access in dual channel provided that the computer is well equipped with an even number of barettes memory and sufficiently analogues in their characteristics (same capacities and rather close standards).

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