AMD64

AMD64 is the name of the architecture of the first Microprocesseur S 64 bits of the company Advanced Micro Devices. Its code name is Hammer (of the English hammer ) replacing name x86-64.

This architecture is compatible with the standard 32 bits X86 of Intel. It is used by the Athlon 64, Athlon FX, Athlon X2, Sempron 64, Turion and Opteron.

Intel adopted this architecture thereafter, under the name of Intel 64, EM64T or IA-32e , in its recent processors of type Pentium 4, Pentium D, Pentium Extreme Edition, Celeron D, and Xeon. Microsoft communicates on this technology under the name of x64.

Dirk Meyer, engineer having worked on the Processor S Alpha from DEC, took part in the project.

Structure

The instruction set of architecture AMD x86-64 is an extension of the Intel architecture IA-32 (x86-32). The principal characteristics of architecture AMD64 is the support of general registers of 64 bits, of arithmetic of the entireties and the logical operations 64 bits as well as virtual addresses 64 bits. The creators benefitted from the architecture appropriateness new to propose other improvements, including mainly:

  • complete Support of the entireties 64 bits : all general registers (GPRs: General Purpose Registers) pass from 32 to 64 bits and all the logical and arithmetic operations, from the memory towards the registers and the registers towards the memory, etc are available nativement for the entireties 64 bits. The push (stacking) and the pop (dépilement) on the pile are always of a width of 8 bytes (64 bits), just as the pointers.

  • additional Registers : the number of the general registers is doubled to reach 16. There needs consequently less to safeguard the registers, to restore them and more generally to handle them; the majority of the arguments of the majority of the functions can in the same way passed by the registers rather than on the pile. As comparison architecture PowerPC 970 has 32 GPRs. The size and the number of register are indeed one of the points weak of the X86. With optimized applications, one can await a performance profit, in particular for the programs having many loops.

  • additional Registers XMM : in a similar way, the number of registers XMM (used for the instructions SIMD) is also increased by 8 to 16.

  • larger virtual Memory capacity : the models of processors currently implementing architecture AMD64 can address up to 256 tebioctets of address virtual memory (248 bytes). This limit can be wide in future implementations with 16 exbioctets (264 bytes). This can be compared with the 4 gibioctets for architectures x86 32bits.

  • larger physical Memory capacity : the models of processors currently implementing architecture AMD64 can address 1 tebioctet of physical address memory. This limit can be wide in future implementations with 4 pebioctets (252 bytes) (limited by the format of the entries of the table of page). In Legacy mode (compatible mode x86), extension PAE (Physical Address Extension) is supported, as on the processors x86 32 bits more running, authorizing the access to a maximum of 64 gibioctets.

  • Accesses to the data relating to the pointer of instruction : the instructions can from now on refer the data relatively pointer of instruction (register RIP). This makes it possible to generate code independent of the position of the program in memory (PEAK, or Position Independent Code) more effective; this is often used in the divided libraries or the code charged with the execution.

  • Instructions SE : architecture original AMD64 adopted the instructions SE and SE within the heart of the processor. The instructions SE were added in April 2005. SE replaces the instruction set X87 of 80 bits of precision, including the choice of floating mathematical operations into 32 or 64 bits. This allows operations in floating decimal point compatible with other CPUs modern. Instructions SE and SE were also extended to support the doors new registers XMM. SE and SE are available in 32 bits on the modern processors x86; however if they are used by programs 32 bits, the latter will be able to function only on processors supporting these instructions. This is not a problem for programs 64 bits, owing to the fact that all processors AMD64 support these instruction sets. To use instructions SE and SE instead of the x87 then does not reduce the number of platforms on which the programs will be able to function. Owing to the fact that instructions SE and SE are generally faster and provide the same functionalities as the plays MX and 3DNow!, the latter are regarded as exceeded on AMD64.

  • No-Carries out bit : bit “NX” (bit 63 of the entries of the table of the pages) allows the operating system to specify which pages of address virtual memory can contain achievable code and which pages cannot it. An attempt to carry out code of an identified page as “No carries out” will cause a violation of access report, identical to that generated at the time of an attempt at writing on a page in " mode; reading seule". This should make more difficult for a malicious code to take the control of the system via the attacks by " buffer overrun" or related to problems of checks of the plugs report. An identical functionality was already available on the processors X86 since the 80286 using an attribute of the descriptors of segment, but can then apply only to one whole segment. Addressing by segment is regarded as obsolete for a long time and all the current operating systems for PC do not use it indeed, while placing the basic address of each one of them to 0 and its size with 4 gigabytes. AMD was the first salesman of the x86 family to support the nonachievable access in mode of linear addressing. This functionality is also available in mode “legacy” on processors AMD64, as well as the processors recent Intel x86, with the use of the mode PAE.

  • Suppression of old functionalities : a certain number of functionalities of programming system of architecture x86 not used in the modern operating systems are not available any more on AMD64 in " length mode". This includes addressing report segmented (although segments FS and GS remain, for compatibility with the Windows code), the mechanism of change of tasks ( task switch ) and the virtual Mode 8086. These functionalities remain in " legacy mode" , to allow these processors to completely carry out codes 32 and 16 bits without modification. If, in the future, should not remain any more of code 32 bits using these functionalities, their support could be removed processors to improve the design of the processors and to save on the production costs. These functionalities could moreover be emulated by the operating system to preserve compatibility with the " applications; legacy".

Various operating processes

Description of these modes

  • Long Mode: native mode 64 bits with compatibility 32 bits (of the not recompilés programs can be used without notable loss of performance). It requires a Operating system 64 bits like GNU/Linux, BSD S, Solaris 10 or Windows XP Pro x64.

  • Legacy Mode: in this mode the Processeur functions classically with the instruction set X86, with all the preceding operating systems like MS-DOS and Windows not 64 bits.

Implementations

The following processors implement architecture AMD64:

See too

External bonds

  • Technical documentation of architecture AMD64 (in)

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